Complexity continues to explode as designs become larger and more complicated with more functionality and more aggressive expectations. The cost of doing business as usual, for the entire design and verification team, in turn, grows exponentially, in terms of time, effort, and dollars.
Fig. 1: Discovering issues later than possible requires more effort to find and fix. (Source: Wilson Research Group and Siemens EDA, 2020 Functional Verification Study)
A significant, but largely overlooked cause of bloated budgets and schedule delays are design errors that could be corrected during design. These bugs don’t require elaborate testbenches and knowledge of esoteric verification technologies to correct. Yet, when passed on to the verification and integration teams, these bugs bring the design flow to a pause, forcing verification engineers to send the buggy blocks back to design engineering.
The best way to fix this problem is at the source, during the design of blocks and sub-blocks. If you can eliminate a bug early when its easy, during design, debug becomes less of a challenge. The trick is that, in order to do so, designers will have to change the way they see and treat verification and debug, and they need the tools to help them do so with minimal effort. They need a set of tools that accelerate their ability to hand over a reasonable quality product to the verification team, so that the verification engineers can bring the block up, integrate it, and be fairly confident they will be able to at least begin the initial integration work and run test cases.
The trouble with tribbles
In the most recent Wilson Research Group Functional Verification Study (2020), designer errors were a major cause of respins in both ASICs and FPGAs. Many of these bugs are the type that could be easily caught by designer-centric solutions. The survey also shows that debug is the biggest time sink, and logically, debug time is a function of how many bugs there are.
Fig. 2: Design errors continue to be the leading cause of functional flaws. (Source: Wilson Research Group and Siemens EDA, 2020 Functional Verification Study)
The explosion of design capture bugs is only getting more troublesome. This is a function of the familiar by-product of electronic design evolution: ever increasing complexity. Not just larger, more jammed packed designs, but larger design teams and more blocks in a design. As designs and design teams scale, so does the snowball effect of design phase bugs escaping from the design to the verification and integration stages.
In simpler times, so to speak, design teams were able to absorb the costs and find workarounds to keep the verification ball rolling forward. The mindset of designers was to get their design work done as quickly as possible and pass it on to the verification team. As long as any testing they did showed that the design was correct per the spec, they were satisfied. They weren’t concerned with 100% coverage. They just wanted to make sure it was correct. Yet, we know the inevitability of missing those hard to uncover bugs lurking in the far corners of our RTL—even when the code matches the spec.
When design capture bugs are found by the verification team, they have to either spend cycles debugging themselves or send it back to the designers. In both instances, the hits on time to tape out and design quality are inevitable and costly. And as we’ve already seen, the Wilson Survey shows these costs are increasing dramatically and causing a drag on the entire design and verification process.
The fix begins with a change in how design engineers think and work. Designers need tools they can use to fix these bugs early, during design, when they are easier, quicker, and cheaper to fix. It is a lot cheaper to find a bug when you’re coding it. In order for this strategy to work, these tools must be easy to set up and not require verification expertise, and designers must be able to run them with minimal effort.
Such a design focused solution addresses the amount of time it takes for verification groups today to bring up a subsystem or a design after integration. Anything you can do early on significantly accelerates things that are happening later.
Nipping bugs in the bud
Sadly, we’re seeing more and more bugs found later in that flow because we haven’t been building tools, as an industry, specifically for the design phase. We built great verification tools, but traditionally CDC, RDC, and other functional verification tools were not built for the designer. Linting is an exception to that rule, but no one has put all these technologies together. So there is a need to bring all these technologies together in a common environment and methodology aimed at the designer.
Teams should not have to wait for a testbench. Instead, they should stop design bugs at the source because fixing bugs before verification yields consistency, efficiency, and predictability.
Fig. 3: Questa Design Solutions produce designs that are correct-by-construction, prove designs meet designer’s intent, and protect designs throughout development.
This is why Siemens EDA has brought together a series of technologies focused on the designer. Questa Design Solutions is a targeted set of verification tools for design engineers, enabling designers to verify as they design. It provides an easy-to-use designer cockpit with a common database that can be moved onto verification and includes the ability to validate the assumptions that have been made. These design focused technologies will tell a designer when something is definitely wrong, without having to burn time on testbench set up. Designers can now ensure good enough quality going into verification, so, in turn, the verification team can get up and running very quickly.
Questa Design Solutions are a set of tools that are optimized for the designer. Its focus is on designers getting the data that they need, both to ensure their design is good and that they have a way of codifying the handoff between design and verification. The ultimate idea is that you build the right design, you make sure the design is okay, and then as the design moves through the development cycle, it stays working. That information is fed forward into verification.
It help designers find the easy bugs, so that verification engineers are not wasting expensive and long simulation cycles finding these design capture bugs. The corollary to that is: the cheapest bug to fix is the one that you never had. If you can catch the bugs in design, you don’t have to find them and fix them in simulation. This not only saves time and effort, but also increases design quality. If we accelerate verification bring up with higher quality, the verification engineers have more time for functional and coverage verification, because they’re no longer doing busy work.
This approach will help instill a new mindset in designers that seeks to illuminate bugs early. It supports this by providing a set of tools designed for ease of use for designers, working in a consistent UI and a consistent database with a way of codifying their assumptions and pushing that design knowledge to the verification team. This leads the way for the verification team to use that data, get verification up and running much earlier, and as a result, be much more effective.
In our next article in this series, due to run in this space in November, we will describe how we meet the necessary goals of this design debug solution.